1. Field of the Invention
The invention relates generally to integrated circuits having repeated logic and interconnect structures provided therein. The invention relates more specifically to providing time-shared access to limited interconnect resources within field programmable gate arrays (FPGA's).
2a. Cross Reference to Related Applications
The following co-pending U.S. patent applications(s) are owned by the owner of the present application and their disclosures are incorporated herein by reference:
(A) Ser. No. 08/948,306 filed Oct. 9, 1997 by Om P. Agrawal et al. and originally entitled, "VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS"; PA1 (B) Ser. No. 08/996,361 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "SYMMETRICAL, EXTENDED AND FAST DIRECT CONNECTIONS BETWEEN VARIABLE GRAIN BLOCKS IN FPGA INTEGRATED CIRCUITS"; PA1 (C) Ser. No. 08/995,615 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "A PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS"; PA1 (D) Ser. No. 08/995,614 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "INPUT/OUTPUT BLOCK (IOB) CONNECTIONS TO MAXL LINES, NOR LINES AND DENDRITES IN FPGA INTEGRATED CIRCUITS"; PA1 (E) Ser. No. 08/995,612 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "FLEXIBLE DIRECT CONNECTIONS BETWEEN INPUT/OUTPUT BLOCKs (IOBs) AND VARIABLE GRAIN BLOCKs (VGBs) IN FPGA INTEGRATED CIRCUITS"; PA1 (F) Ser. No. 08/997,221 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, "PROGRAMMABLE CONTROL MULTIPLEXING FOR INPUT/OUTPUT BLOCKs (IOBs) IN FPGA INTEGRATED CIRCUITS"; PA1 (G) Ser. No. 09/008,762 filed Jan. 19, 1998 by Om P. Agrawal et al. and originally entitled, "SYNTHESIS-FRIENDLY FPGA ARCHITECTURE WITH VARIABLE LENGTH AND VARIABLE TIMING INTERCONNECT"; and PA1 (H) Ser. No. 08/996,049 filed Dec. 22, 1997 by Om P. Agrawal et al. and originally entitled, "DUAL PORT SRAM MEMORY FOR RUN-TIME USE IN FPGA INTEGRATED CIRCUITS. PA1 (A) U.S. Pat. No. 5,212,652 issued May 18, 1993 to Om Agrawal et al, (filed as Ser. No. 07/394,221 on Aug. 15, 1989) and entitled, PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE; PA1 (B) U.S. Pat. No. 5,621,650 issued Apr. 15, 1997 to Om Agrawal et al, and entitled, PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES; and PA1 (C) U.S. Pat. No. 5,185,706 issued Feb. 9, 1993 to Om Agrawal et al.
2b. Cross Reference to Related Patents
The following U.S. patent(s) are related to the present application and their disclosures are incorporated herein by reference:
3. Description of the Related Art
As density within integrated circuits (IC's) of digital logic circuitry increases, and as signal processing speed of such logic also increases, the ability to couple respective signals to an appropriate kinds of interconnect resource becomes more difficult.
Artisans have begun to recognize that conductors of different lengths and orientations should be provided for servicing different kinds of signals in programmable logic arrays. By way of example, a first class of relatively long and relatively low-resistance conductors are included for broadcasting common control signals (e.g., clock, clock enable, etc.) over relatively large distances of the IC device with minimal skew. Such special conductors are sometimes referred to as low-skew longlines.
As a further example, some wire segments are dedicated for transmitting logic input and logic output signals between immediately adjacent logic sections without routing through general switch matrices. These dedicated conductors are sometimes referred to as direct-connect lines.
At the same time that specialized conductors are provided, artisans strive to continue to provide field programmable logic arrays with general-purpose conductors and general-purpose routing switches for carrying out general-purpose, programmable routing of signals.
With all different kinds of conductors competing for space within the interconnect layers of an IC, the numbers of conductors for each kind of specialized interconnect resource (e.g., longlines) at each location becomes a relatively limited resource. Every signal within a complex design cannot be allowed to have its own dedicated interconnect line. If it were otherwise, the limited interconnect resources of the field-programmable array device would soon be exhausted. Fortunately, many designs allow for the transmission of plural signals at different times over a shared interconnect line. Such sharing may come in the form of time-domain multiplexing or burst-mode operations.
A number of different circuit techniques have been developed for allowing multiple signals to share a same interconnect line. Multiple tristate drivers may be used for example, with each tristate driver becoming a line master at a different time while the other tristate drivers of the same line go into a high-impedance output mode. The line-driving signal of that moment then passes without contention onto the shared line through its line-mastering, tristate (three state) driver.
In an alternative approach, a shared wire is urged towards a predefined logic state by means of a pull-up or pull-down resistor. An open-drain technology is then used to implement a wired-OR circuit on the urged line. Sharing signals OR into the shared line at different times. If desired, a logical ORring of simultaneous signals may be carried out on the so-driven line.
A third approach provides a dedicated multiplexer for driving the shared line. At each given time, an appropriately desired signal is selected by the dedicated multiplexer for output onto the shared line.
Each of these approaches has drawbacks. Tristate drivers tend to consume more circuit area than two-state drivers. They also generally need specialized control circuits for controlling their output-enable (OE) terminals so that contention and crowbar currents will be avoided. Wired-OR circuits tend to consume more power than purely CMOS circuits. Dedicated multiplexers are wasteful if it happens that their full selection capabilities are not utilized in a given design implementation.